1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device and a method for fabricating the same, to obtain high integration in the semiconductor device by scaling a transistor below nano degree.
2. Discussion of the Related Art
In case of a general MOS device, a gate is formed on a semiconductor substrate, and impurity ions are implanted to the semiconductor substrate in state of using the gate as a mask, and then a following thermal process is performed thereto, to diffuse the implanted impurity ions, thereby forming source and drain diffusion regions.
However, if the gate has a length below 0.06 μm, the source diffusion region may be connected with the drain diffusion region since the implanted impurity ions are diffused in the following thermal process. In this reason, it is impossible to fabricate a MOS transistor.
Even in case the gate has a length above 0.06 μm, it is impossible to perform a shallow junction between the source diffusion region and the drain diffusion region, below 10 nm. Accordingly, a drain electric field of the MOS transistor may permeate to a channel region, whereby a threshold voltage is lowered. Also, a short channel effect such as a drain induced barrier lowering DIBL may generate.
The alternative to the source and drain diffusion regions in the transistor of nano degree below 0.1 μm is virtual source and drain diffusion regions of using a sidewall gate. The virtual source and drain diffusion regions have been mentioned in “Threshold Voltage Controlled 0.1 μm MOSFET Utilizing Inversion Layer as Extreme Shallow Source/Drain” (H. Noda, F. Murai and S. Kimura in IEDM Tech. Dig., 1993, pp. 123-126), published in 1993.
FIG. 1 is a cross sectional view of an NMOS device having virtual source and drain regions according to the related art.
As shown in FIG. 1, an STI oxide layer 12 is formed in a field region of a p-type semiconductor substrate 11, whereby the p-type semiconductor substrate 11 is divided into the field region and an active region. Then, a main gate 14, highly doped with n-type impurity ions, is formed on a predetermined portion of the active region of the semiconductor substrate 11. Also, a sidewall gate 15 is formed at both sides of the main gate 14, wherein the sidewall gate 15 is formed of highly doped n-type impurity ions.
Furthermore, a main gate insulating layer 13 is formed between the main gate 14 and the semiconductor substrate 11. Also, another insulating layer 16 is formed between the main gate 14 and the sidewall gate 15. In addition, a sidewall gate insulating layer 17 is formed between the sidewall gate 15 and the semiconductor substrate 11.
Then, source and drain regions 18 and 19 are formed at both sides of the sidewall gate 15 in the active region of the semiconductor substrate 11. Also, a main gate line 20a, a sidewall gate line 20b, and source and drain lines 20c and 20d are respectively connected with the main gate 14, the sidewall gate 15, and the source and drain regions 18 and 19.
In case of a PMOS device, it has the same structure as the NMOS device except that the implanted impurity ions are opposite, whereby the explanation for the structure of the PMOS device will be omitted.
In the NMOS transistor, when a predetermined voltage is applied to the sidewall gate 15, an inversion layer is formed in the semiconductor substrate 11 below the sidewall gate 15. At this time, the inversion layer functions as virtual source and drain regions 18a and 19a, which correspond to the lightly doped source and drain regions of the MOS transistor.
On applying a predetermined voltage to the main gate 14, a channel is formed in the semiconductor substrate 11 below the main gate 14, whereby a current flows between the virtual source region 18a and the virtual drain region 19a. 
As shown in the drawings, the related art MOS device requires the sidewall gate line 20b as well as the main gate line 20a, to apply the predetermined voltage to the sidewall gate 15. In this state, according to the increase of integration, it is difficult to form the sidewall gate line 20b. 
During a silicide process, the sidewall gate 15 and the main gate 14 may be short. Also, since there is requirement for insulating the main gate line 20a from the sidewall gate line 20b, it is difficult to scale the MOS transistor below nano degree.